IEEE Standard for High-Speed Test Access Port and On-Chip Distribution Architecture
NORMA vydána dne 28.7.2017
Designation standards: IEEE 1149.10-2017
Publication date standards: 28.7.2017
The number of pages: 96
Approximate weight : 319 g (0.70 lbs)
Country: International technical standard
Kategorie: Technické normy IEEE
New IEEE Standard - Active.
Circuitry that may be built into an integrated circuit to assist in the test, maintenance, and support of assembled printed circuit boards, assembled multi-die packages, and the test of die internal circuits is defined in this standard. The circuitry includes a high-speed TAP (HSTAP) with a packet encoder/decoder and distribution architecture through which instructions and test data are communicated. The standard leverages the languages of IEEE Std 1149.1™ to describe and operate the on-chip circuits.
ISBN: 978-1-5044-3995-4, 978-1-5044-3996-1
Number of Pages: 96
Product Code: STD22564, STDPD22564
Keywords: 3D-IC, Boundary-Scan Description Language, BSDL, debug, High Speed JTAG, I2C, IEEE 1149.1™, PDL, IEEE 1149.10™, integrated circuit, JTAG, wafer, Procedural Description Language, SERDES, SPI, system level test
Category: Test Instrumentation and Techniques|Test Technology